The present invention relates to an output buffer circuit that can suppress skewing.
In recent years, as the transfer rate of data exchanged between two chips has been increased, it has become increasingly important to minimize skewing between a clock signal and a data word transmitted or between two data words transmitted.
In the pertinent prior art, if data words should be transferred at a high rate, skewing, or a phase difference between two signals, has been suppressed by synchronizing the output time of a clock signal with that of a data word using DLL, PLL or the like.
However, the present inventors found that only by synchronizing output times of clock signals and data words as in the prior art, skewing still happens after the synchronization and data words cannot be received just as expected due to skewing if data words are transferred at an even higher rate.
And we found that skewing still occurs after the synchronization of output times, partly because an interval, during which a signal to be transmitted remains in the same logical state (in this specification, such an interval will be called a "stable-state interval"), is of a variable length. Hereinafter, this point will be discussed in greater detail with reference to FIG. 5.
In FIG. 5, CLK denotes a clock signal; Dout1 and Dout2 respective data words output from a driver to a bus on the transmitter end; and Vref a reference voltage used for determining the logical states of data words on the receiver end. The receiver determines a voltage lower than the reference voltage Vref to be L level and a voltage higher than the reference voltage Vref H level. The level of the data word Dout1 starts to rise from L to H in synchronism with the falling edge (time) T1 of the clock signal CLK, and is held at L during an interval preceding the time T1. As can be seen, the data word Dout1 has a long stable-state interval. On the other hand, the level of the data word Dout2 starts to fall from H to L in synchronism with the rising edge (time) T0 of the clock signal CLK, and starts to rise from L to H in synchronism with the next falling edge T1. Accordingly, the interval before the time T1, during which the data word Dout2 is at L level, is relatively short. That is to say, the data word Dout2 has a relatively short stable-state interval. The potential level of the data word Dout1 starts to rise from an L-level potential VL at the time T1 and then reaches an H-level potential VH. In contrast, the potential level of the data word Dout2 starts to fall from the H-level potential VH at the time T0, but does not quite reach the L-level potential VL at the time T1. Instead, at the time T1, the potential level of the data word Dout2 starts to rise from a level higher than the L-level potential VL by a predetermined potential difference Vd. Thus, it takes a longer time for the level of the data word Dout1, having a longer stable-state interval than that of the data word Dout2, to reach the reference voltage Vref from the time T1 as compared with the data word Dout2. In other words, a time lag (i.e., skewing) SKt exists between these data words Dout1 and Dout2. The higher the frequency of the clock signal CLK is and the heavier the load on the bus for transmitting these data words is, the more remarkable this skewing SKt is. As can be understood, even if two data words Dout1 and Dout2 are output at the same time from a driver on the transmitter end, skewing still happens due to a difference in length of the stable-state intervals of these data words.